Validation Engineering & Semiconductor Design Intern

Key Responsibilities

Hardware Validation

• Validated 800G Ethernet PHYs with 112G PAM4 SerDes for high-speed data centers
• Designed test scenarios using Pytest to ensure IEEE standards compliance
• Deep knowledge gained in Error Detection, Ethernet Frames, and OSI model
• Focus on MAC & PHY layers, particularly PCS (Physical Coding Sublayer)

NASA HPSC Training

• Received training on NASA's High-Performance Spaceflight Computing (HPSC) project
• SystemVerilog for hardware verification
• Fault-tolerant systems to mitigate SEUs (Single-Event Upsets)

Skills Gained

• Large-scale project management
• Hardware design and fault injection
• Regression testing methodologies
• Git and CI/CD pipelines
• Extensive Linux experience for deployment, testing, and system management